A New Architecture Drives the Competitiveness of Next-Generation Storage
What do you currently do at AIO?
I am responsible for Firmware development for next-generation storage products within Solution Development Team 2. AIO is expanding into new business areas with next-generation storage products such as UFS and cSSD, building on its SD Card and eMMC Controller technologies.
My work can be divided into two main areas. The first is designing and developing Firmware architecture for new products. Because these products must meet significantly more demanding performance and specification requirements than existing products, the work goes beyond simply improving the existing architecture—it is closer to designing a new architecture from the ground up.
The second is pre-silicon verification during SoC development. Through simulation, I analyze whether the hardware being designed by the SoC Team can achieve the target performance and determine what additional hardware components and automation features may be required. I then provide feedback so that these findings can be reflected in the design. Because design changes become difficult once the chip has been fabricated, predicting and verifying performance during the design stage is critical.
What skills or capabilities do you consider most important in your role?
I believe the most important capability is the ability to design a Firmware architecture and optimize it until the target performance is achieved.
In high-performance storage, performance does not depend simply on how well individual parts of the code are written. It is largely determined by how the architecture is designed from the outset. Early decisions—such as how to structure the command-processing pipeline, which tasks should be handled by hardware and which by Firmware, and how to design interfaces and data flows between modules—ultimately determine the performance limits of the system. A well-designed architecture can deliver further performance gains through continued optimization.
This requires the ability to view the entire system from a performance perspective. You need to trace the data flow from the Host Interface through the Firmware command-processing architecture and NAND channel parallelization to hardware acceleration blocks in order to accurately identify bottlenecks.
A solid understanding of storage protocols such as eMMC, UFS, and NVMe is also important, along with Flash management techniques such as FTL, Wear Leveling, and Garbage Collection, and C-based embedded programming skills. In addition, the role requires simulation capabilities to model hardware that has not yet been implemented and predict its performance, as well as the ability to communicate analysis results so that the SoC Team can directly apply them to the design.
What has been your most rewarding experience?
One of my most memorable experiences was analyzing the NAND Interface operation of a next-generation Controller.
The technical descriptions of the page layout and data reliability mechanisms differed slightly across documents, creating a risk of data consistency issues if they were implemented as written. I therefore re-analyzed the specifications from the beginning and verified the actual behavior step by step to clearly define the architecture. I then documented the results as a technical reference for the team, providing a common basis for everyone involved in subsequent development.
Developing a new product means continuously encountering problems for which there is no precedent to follow. I find it most rewarding when we build up evidence step by step in areas where no one yet knows the answer, establish a new technical standard, and see that work become a lasting technical asset for the team.
What would you like to achieve at AIO?
My goal is to complete the Firmware architecture for next-generation storage products that will drive AIO’s growth over the next decade.
UFS and cSSD products require performance levels tens of times higher than those of conventional eMMC, which means moving beyond sequential command-processing architectures to a new architecture capable of delivering both high parallelism and low latency. I want to build a robust architecture that is not limited to a single product, but can serve as the foundation for future product development.
I also want to establish performance simulation and verification at the design stage as a standard process within the team. If we can accurately predict performance before chip fabrication, we can significantly reduce development risks and shorten development cycles. By actively applying AI-based tools to repetitive analysis and verification tasks, I hope to help create a development culture in which engineers can focus more on design decisions and problem solving.
What advice would you give to those preparing to join AIO?
AIO continues to create new products and markets based on next-generation storage technologies. For this reason, when you encounter an unfamiliar problem, the habit of investigating it thoroughly based on documentation and data is far more important than simply finding a predefined answer quickly.
Building strong fundamentals in C, operating systems, and computer architecture—and gaining experience analyzing systems from a performance perspective—can be a significant advantage.
The storage field also offers many publicly available specifications, including eMMC, UFS, and NVMe, giving students plenty of opportunities to gain relevant experience. Reading and interpreting specification documents yourself, or building simple simulators and analysis tools, can be particularly valuable.
If you are eager to take on the challenge of exploring new areas, I believe you can help shape the future of next-generation storage technology at AIO.